No Commercial EDA Tool Supports Glass Interposers. We Built One.
Cadence Sigrity, Synopsys, Ansys HFSS — none of them support glass substrates as a first-class citizen. Engineers designing for Intel Foveros 2026 and TSMC InFO-Glass 2028 are flying blind. Here is the platform we built to fill the gap, and why nothing else can do it.
The deadline that nobody is meeting
Intel announced glass core substrates for Foveros packaging in 2026. TSMC's InFO-Glass program targets 2028. Samsung, SK hynix, and ASE are following with their own glass roadmaps. The substrate transition from organic and silicon to glass is happening, and the foundries have committed capacity dollars to it.
The problem is that the design tools have not made the same transition. Engineers writing PDKs, signoff flows, and DRC decks for Foveros 2026 are doing it with EDA tools that have no native glass material library, no through-glass via models, no panel warpage solver, and no glass-to-glass bonding yield model. They are extrapolating from silicon TSV rules and hoping the physics translates. It does not.
What is missing in the incumbents
TGV impedance models
Through-glass vias have different impedance characteristics than through-silicon vias. The dielectric is 5-10x higher resistivity, which changes the loss tangent. The aspect ratio is different. The pad parasitics are different. None of the commercial 3D EM tools ship with a TGV impedance solver — you have to build the geometry by hand and run a 3D FEM simulation that takes hours.
Glass-specific dielectric data
Cadence Sigrity, Synopsys, and Ansys all ship material libraries. None of them include Corning Eagle XG, Corning Lotus NXT, AGC EN-A1, SCHOTT AF32, or fused silica. To use these glasses you have to enter their dielectric properties manually, with no dispersion data, no anisotropy data, and no validated reference measurements.
Panel warpage solvers
Glass panels are rectangular, not round. They warp differently from circular wafers — the von Karman nonlinear plate equations are required for accurate prediction. Cadence and Synopsys do not solve plate equations at all. Ansys can, but only if you build the geometry yourself, mesh it, and run a multi-hour static analysis per design point.
Glass-to-glass bonding yield
Hybrid bonding yield depends on surface roughness correlation length, contact mechanics, and void formation kinetics. The physics is well understood in the literature, but no commercial EDA tool implements it. Engineers doing yield prediction for glass interposers fall back to either spreadsheets or Monte Carlo simulations they wrote themselves.
What Genesis ships
We built the platform that fills the gap. Specifically:
- A boundary element method TGV impedance solver calibrated to 4.0% mean abs error against 6 in-scope coaxial-TGV papers. Runs in under 10 ms per design point on CPU.
- A 2.95M-row live BEM simulation corpus plus a 15.92M-row ML table covering glass compositions, metal systems, and frequency bands. Every row sourced and traceable.
- 995 active curated unique Touchstone S2P assets, ready to drop into Sigrity, HFSS, or Keysight ADS for final signoff.
- A Kirchhoff-von Karman panel warpage solver that handles rectangular substrates natively. Validated against 30 NLGEOM FEM cases at 0.000% azimuthal artifact.
- A KLA Archer calibrated bondability yield model. Ten wafers of overlay metrology lock the parameter. Real-time inference in 13 ms on CPU.
- Eight Golden Kits for UCIe @ 32 GT/s, DDR5 @ 6.4 Gbps, PCIe Gen6, 400G SerDes, WiFi 7, automotive radar, HBM4, and a custom kit. Each is a one-page YAML spec that compiles to GDSII in under one second.
Head-to-head capability matrix
| Capability | Genesis | Sigrity | Synopsys | HFSS |
|---|---|---|---|---|
| Glass material library | Yes (12) | No | No | No |
| TGV impedance solver | 10 ms BEM | 3D FEM (hours) | No | 3D FEM (hours) |
| Panel warpage (rectangular) | Cartesian FEM | No | No | Manual |
| S2P library (glass) | 2,434 files | DIY | DIY | DIY |
| Hybrid bonding yield | FNO 13 ms | No | No | No |
| End-to-end pipeline | 1 API call | No | No | No |
Why incumbents have not built this
Glass interposer is a small market today and a large market in three years. Incumbents have not built support because the ROI is back-loaded — they are revenue-optimizing for the silicon installed base. Genesis is small enough to bet on the inflection point and patient enough to ship the tools before the market demands them.
The technical moat is the BEM solver, the 15.92M-row multiout corpus, the IEEE calibration, and the 995 active curated unique S2P assets. None of those can be assembled in a quarter. The first commercial EDA vendor that wants to ship glass support has to either spend years building the same physics or license what we have already built.
Bottom line
Genesis is the only end-to-end design-to-yield platform for glass substrate chiplet packaging. If you are designing for Intel Foveros 2026 or TSMC InFO-Glass 2028, you do not have another option. See the glass interposer solution page for the full pipeline, or try the playground to run the BEM solver yourself.