Solution · Silicon photonics
Silicon photonics signoff in your AI workflow
Closed-loop synthesis, multi-solver verification, cross-EDA export, and AIM-Photonics-class DRC for photonic IC designers — under the same audit gates as the ChipletOS chiplet stack.
What we address
Four pain points photonic IC teams hit today
Closed-loop synthesis
Target Neff / FSR / Q → recovered geometry in one API call. Differentiable closed-form analytical hot path means inverse design fits in an optimizer inner loop today; the trained AI surrogate v1 (5 of 6 primitives, ≥ 99% R² vs our reference solver) tightens agreement on MZI / MMI / ring / grating / photonic crystal. Higher-fidelity refresh on the roadmap.
Multi-solver verification
Full-wave reference solver (truth) + cross-physics solver + closed-form analytical (fast) under one signoff matrix. Same pattern as the chiplet 4-solver matrix (BEM + FastHenry2 + OpenEMS + Palace) that ships today.
Cross-EDA export
Lumerical / Omnisim / GDSII exporters scaffolded. Customer-side native validation deferred (requires Lumerical / Photon Design license) — same workflow-lock posture as the 5/5 chiplet cross-EDA exporters (Cadence Sigrity / Synopsys SiP / Keysight ADS / Siemens HyperLynx / Ansys HFSS).
Honest validation suite
Five new photonic validation-suite checks: AI surrogate R², AIM-class DRC, cross-solver agreement, published-paper cross-check, adversarial robustness harness. The DRC, published-paper cross-check, and adversarial harness pass live today; the surrogate-R² and cross-solver checks are on the roadmap as the reference corpora and cross-physics binary land.
Customer archetypes
Who this is built for
Marvell SiPh
Datacenter silicon-photonics for 800G / 1.6T optical interconnects. Surrogate-fast Neff + ring-resonator synthesis for high-iteration WDM design.
Intel Foundry photonic
Foundry-side photonic PDK customers. The same closed-loop synthesis + AIM-class DRC pattern they already need on the chiplet stack.
NVIDIA optical
Co-packaged optics R&D. Photonic inverse design alongside the chiplet BEM stack — one platform, one signoff API.
Acacia (Cisco)
Coherent transceiver IC teams. MZI + grating coupler signoff under the same audit gates as chiplet RF.
Lumentum
Photonic component vendors needing fast Pareto exploration over (FSR, Q, footprint, insertion loss) on ring resonators + couplers.
Differentiation
AI-EDA distribution layer + cross-vendor exporters + honest gates
We are not trying to out-Meep Meep. We are wrapping the truth-grade solvers with the AI-EDA distribution and audit surface that the EDA incumbents do not ship.
vs Lumerical
Lumerical is the truth-grade FDTD solver; ChipletOS Photonic Signoff is the AI-native distribution layer. We don't replace Lumerical FDTD — the trained AI surrogate v1 ships at ≥ 99% R² vs our reference solver for 5 of 6 primitives (higher-fidelity refresh on the roadmap) and we wrap it with an inverse-design + cross-vendor-export API surface that Lumerical does not ship.
vs Synopsys-Lumerical
Synopsys owns Lumerical (~$80M photonic EDA revenue) but has no AI-EDA distribution story for it. ChipletOS Photonic Signoff plugs into the same AI-EDA distribution surface (MCP, Cursor, Claude.ai skills) that the chiplet stack already uses.
vs Photon Design Omnisim
Smaller incumbent. We export to Omnisim format and treat them as a partnership candidate rather than an acquisition target.
vs the rest of the EDA stack
Cadence + Mentor + ANSYS have no photonic-IC tool of significance. Same dynamic as glass-TGV in chiplet — a real coverage gap, not a marketing one.
Trust posture
See Trust & Validation for the full validation-suite methodology and our published-paper cross-check numbers.
Ready to design photonics in your AI workflow?
The same audit pattern, same surrogate stack, same cross-vendor exporter discipline as the ChipletOS chiplet stack — applied to silicon photonics.