The Operating System for Chiplet Manufacturing
Computational physics for substrate-agnostic advanced packaging (glass, organic ABF, silicon interposer, ceramic). Impedance, isolation, yield, and design signoff — validated against four independent solvers. One API. One audit trail.
Only parameterized glass-TGV PDK in existence
Cadence Sigrity, Ansys HFSS, Synopsys, and Mentor have no glass substrate support. HFSS adds glass in 2026 roadmap; Sigrity Q4 2026. ChipletOS ships today with 4 substrate classes + 21 materials, 6.75M-row group-disjoint corpus, and route-backed signoff.
ChipletOS Photonic Signoff (alpha)
Sister sub-brand. Silicon-photonics IC signoff under the same validation suite as the chiplet stack — 6 primitives (waveguide / MZI / MMI / ring / grating / photonic crystal), 40 total /v1/photonics/* surface incl. PROV4 RF, AIM-Photonics-class DRC, AI surrogate live for 5 of 6 primitives at R² ≥ 0.99 vs reference solver; waveguide on closed-form analytical fallback. One platform, two markets. Try the live waveguide predictor.
4-solver cross-validated
BEM + FastHenry2 + OpenEMS + Palace FEM converge on Z₀ across 25 signoff geometries. 4.0% mean abs error vs 6 IEEE-published references. Palace full-wave FEM provides independent cross-physics truth (100 runs across 28–200 GHz). No EDA vendor offers a 4-solver witness matrix.
290 production /v1 routes · audit-grade lineage
11 file-ready patent bundles, 39 retractions documented, 5/5 cross-EDA-vendor exporters (Cadence Sigrity / Synopsys SiP / Keysight ADS / Siemens HyperLynx / Ansys HFSS) + Sprint 54 additions (LEF/DEF + OASIS + Verilog-A EPDA tool + Photo-Elastic Waveguide Router) with 380+ adapter-cell verifications, drift-sentinel + scanner pipeline catches drift in CI. Buyer plugs into internal flow day 1; integration cost zero.
GDS-to-yield in one workflow
7-stage hybrid-bonding yield pipeline: CMP recess → contact mechanics → anneal → warpage → stress → diffusion → yield. 33-defect IPC/SEMI/ISO taxonomy + 12 CAPA patterns + 811K WM-811K-labeled wafer images. KLA Kiyo is post-fab inspection only — nobody else closes the design-to-fab loop.
Real route-backed signoff. Live alias. Hashed witnesses.
The dashboard at app.chipletos.com runs the production surrogate model — R² 0.9999966 / 0.029% MAPE on a geometry-disjoint 6.75M-row test set — against 60 route-backed package signoff cases (RF + isolation + yield in series) and surfaces the 4-solver cross-solver witness, the deep ensemble CI band, and the OOD flag for every prediction. Every number renders from a SHA-256-hashed manifest.
Where ChipletOS leads. Where competitors still own.
Honest snapshot vs the four major EDA platforms. The differentiator is not "we beat them at HFSS" — it's that no commercial parameterised glass-TGV PDK exists on the market and ChipletOS is the only platform that ships one. Competitors lead on fab data; ChipletOS leads on automation and route-backed signoff.
| Capability | ChipletOS | Cadence Sigrity | Synopsys HSPICE | Keysight ADS | ANSYS HFSS |
|---|---|---|---|---|---|
| Parameterised TGV PDK (4 substrate classes + 21 materials) | Live | absent | absent | absent | absent |
| BEM solver vs 6 IEEE-published HFSS-coaxial reference points | 4.00% MAE (HFSS-coaxial cross-physics; not VNA) | absent | absent | absent | absent |
| 60-case route-backed signoff (RF pass) | 60/60 | absent | absent | absent | absent |
| 4-solver cross-solver witness (BEM + FastHenry2 + OpenEMS + Palace) | Live | Partial | absent | Partial | Partial |
| Per-prediction CI + OOD flag (3-seed deep ensemble) | Live | absent | absent | absent | absent |
| 5/5 cross-EDA export (377+ adapter-cell verifications) | Live | Own only | Own only | Own only | Own only |
| Median signoff cycle time | ~141 ms | hours–days | hours–days | hours–days | hours–days |
Glass Packaging Has Outgrown Traditional EDA
The move to glass interposers and glass package substrates has created a gap that legacy EDA tools do not close. Buyers need a route from package requirements to RF, isolation, yield-risk, and downloadable artifacts instead of stitched-together point tools.
Fragmented Legacy Tools
Legacy point tools still leave glass TGV impedance, isolation, and bondability spread across different assumptions and outputs.
Unified ChipletOS Pipeline
ChipletOS packages Glass PDK, EM Isolation Compiler, and Bondability Pipeline into one route-backed signoff suite with S2P, report, manifest, and provenance.
“We are solving the ‘Physics of the Gap’ —the critical space between the silicon die and the final package.”
From Wafer State to Package Signoff
Follow one continuous operating flow instead of stitching together separate tools for stress, interconnect, isolation, yield, and final customer artifacts.
Wafer Warpage
Model wafer stress early so packaging decisions start from measured deformation, not assumptions.
Kirchhoff plate FEM • sub-4 ms latency
Package Warpage
Track panel-level alignment risk before the stack reaches bonding and assembly constraints.
Panel deformation modeling for large-format substrates
BEM Impedance
Predict glass TGV impedance with the platform's core solver instead of guessing through analytic shortcuts.
3.57% MAE vs IEEE-published HFSS refs • glass TGV impedance PDK
Isolation Synthesis
Design isolation structures that close the loop from field behavior to manufacturable geometry.
EM Isolation Compiler isolation-signoff route • frequency-dependent margining
Yield Prediction
Connect layout, overlay, and contact mechanics to bonding yield before the mask spend lands.
Bondability Pipeline bondability-signoff route • uncertainty + calibration state
Signoff Artifacts
Export the outputs buyers can actually consume: Touchstone content, GDS export spec, report markdown, manifest hash, and provenance.
POST /v1/chiplet-suite/package-signoff • 25/25 route-backed cases • 995 active curated S2P assets
Built for the Hardest Problems in Heterogeneous Integration
Explore Full Capabilitiesarrow_forwardGDS In, Yield Out
The signoff suite connects glass TGV RF, isolation margining, bondability risk, Touchstone output, GDS export specs, and provenance into one package workflow.
Unified API + CLI
Control the entire physics stack through a high-performance Python API or a secure, headless Linux CLI.
Glass TGV Impedance
The only multiconductor TGV impedance tool in existence. 3.57% MAE vs 6 IEEE-published HFSS-coaxial reference points, with a broader 18-point 5.75% RMSE witness and 9/10 geometry checks staying within 2% through 250 GHz. A strict geometry-group four-seed baseline production cohort aggregate now shows mean unseen-geometry R² 0.9751 at 4.59% MAPE on 1.5M-row training runs, with HBM4 remaining the soft regime at 0.9093 / 8.07%.15.92M ML rows plus 901K separately versioned strict buyer-regime additions. Coaxial approximation is 55–225% wrong on glass.
Isolation Synthesis
The only tool that designs isolation structures, not just analyzes them. Adjoint topology optimization to DRC-clean GDSII export in one closed loop.
909 Filed Subclaims / 146 Independent Claims
280 utility filed Jan 2026 + 629 provisional. Provisionals establish priority date but are not yet examined; non-provisional conversion in progress, deadline 2027-01-31. Issued claims to date: 0. Comprehensive IP coverage across BEM impedance, hybrid bonding yield, isolation synthesis, bondability screening, and provenance-bound signoff workflows. Full portfolio under NDA.
Put the proof where it belongs: alongside the evidence, not in the hero.
The current proof layer is not just literature matching. It now includes a 25-case package-signoff benchmark, S2P registry validation, a measured-calibration Bondability Pipeline lane, and a one-command evidence pack tied to the claim trace.
Surrogate accuracy
R²=0.9999966 · 0.029% MAPE
6.75M-row BEM corpus, geometry-disjoint split, 78,840 unseen test geometries. HBM4 test MAPE 0.015%. Every promotion gated by automated CI checks.
Route-backed signoff
60/60 RF pass
HBM4 / UCIe / PCIe Gen6 / 800G / 77 GHz radar across 12 geometry variants. Mean worst Z₀ 1.94%, max 6.73%.
4-solver cross-validation
4.0% MAE vs IEEE · 6.73% BEM-vs-Palace envelope
BEM + FastHenry2 + OpenEMS + Palace FEM independently converge on Z₀. Validated against 6 IEEE-published references (simulation-derived, not VNA). VNA campaign planned.
Per-prediction confidence
95% coverage · ECE 0.79% · OOD on 7 axes
Every API call returns Z₀ + 95% conformal CI band + per-axis OOD diagnostic. Calibrated intervals are empirically correct 94.4–95.4% of the time across all 4 geometry regimes.
Cross-EDA export
5/5 vendors · 377+ adapter verifications
Cadence Sigrity, Synopsys SiP, Keysight ADS, Siemens HyperLynx, Ansys HFSS. Native-format export verified at zero floating-point error across 250 material cells.
Inverse design
r=0.99984 gradient · 8/8 cases pass
Target Z₀ → recovered geometry in one API call. Differentiable surrogate gradient matches BEM physics gradient. No EDA vendor ships an inverse-design endpoint for glass packages today.
Lab readiness score
0–100 · send / QC / hold / reject
Composite score combining cross-solver agreement, conformal CI width, OOD severity, and ensemble uncertainty. Never fabricates proxy values for missing data.
Per-regime calibration heads
6/6 regimes deployed · 5/6 above 80% gap closure · 1/6 near-elite at 76.7% · pooled 86.0%
Per-regime cross-physics calibration heads close the gap between fast quasi-static and full-wave reference solvers. Sprint 45 v2-clean retrain numbers (witness benchmarks/sprint45/post_cal_head_agreement_2026_05_05.json): ULTRA_HIGH_FREQ 92.0% · HBM4 90.7% · WIDE_PITCH 85.9% · MMWAVE 84.7% · UCIE 81.5% · EXTREME_TIGHT 76.7% — pooled 86.0% gap closure (17.10% → 2.39% mean BEM-vs-Palace error). EXTREME_TIGHT is capacity-bound by a 51.7% solver-failure rate on small-pitch geometries — disclosed ceiling, not aspirational. Reference is full-wave Palace FEM, not VNA-measured.
Audit infrastructure
25 §9 gates · 39 retractions · 1121 tests
17 validation suite gates pass at every commit, including the multi-physics cal heads (thermal MAE 1.14 K, mechanical MAE 4.33 µm) trained against CalculiX FEM truth corpora. Plus synthetic-data sniffer, phantom-cite detector, witness-freshness, API-contract drift, patent-bundle integrity, cross-PROV consistency. Buyer-runnable 5-min adversarial harness.
Current proof stack
IEEE-published HFSS-coaxial references and FastHenry2 are the published cross-references; Palace 0.16.0 (real transient FEM, n=100 multifreq) is the strongest non-VNA cross-physics check on this platform. Palace FEM is quoted at the 5 GHz extraction, with 10 of 50 simulations inside ±5% in the core regime.
The expansion lane now cites 901K separately versioned strict additions across the buyer-regime expansion runs. The geometry-challenge replay and strict 1.5M witness are explicit on the site instead of buried in docs, and the active S2P library plus package-signoff route remain available for direct SI workflows.
Executive Strategic Pillars
Predict Yield Before the Fab
The only GDS-to-yield pipeline for hybrid bonding. Seven coupled physics stages predict manufacturability before you commit silicon or glass. No more $500K mask-set surprises.
Design on Glass, Not Guesswork
No EDA vendor ships a glass-calibrated impedance model. Our BEM solver is 55–225% more accurate than the coaxial approximation on TGV geometries. 15.92M rows, 4 substrate classes + 21 materials.
Turn Metrology Into Revenue
Bridge overlay registration data to bonding yield predictions. Make existing KLA Archer data predict yield, not just measure alignment error. The highest-scored claim in our portfolio.
FluxZero — PFAS-free thermal fluid IP for the post-Novec era
Marangoni-active, self-pumping dielectric for two-phase immersion cooling. Same ownership as ChipletOS; separately branded.
Materials IP — 86 provisional drafts. 5 Crown 5. $20B+ TAM.
GAA gate dielectrics, BSA glass substrate, TGV barriers, low-k RDL, ALD chip film, rad-hard glass, TIM, MLCC, and a methods bundle. 33 buyer-mapped provs across Intel · Samsung · TSMC+Corning · Corning · Terafab · Cadence · NVIDIA · AGC/NEG.
Platform Snapshot
The Software Layer for the Chiplet Era
Join the consortium of leaders redefining semiconductor manufacturing.