Buyer packages

Pre-built buyer packages

Each package is a curated slice of the ChipletOS platform tuned to a target buyer’s workflow. Same backend, same evidence chain — different surface.

Corning

arrow_forward

Glass TGV impedance design kit

Eagle XG / SiO₂ / borofloat sweeps with BEM-validated impedance, FastHenry2 inductance cross-check, and touchstone exports.

Intel

arrow_forward

EM isolation for advanced packaging

Closed-loop synthesis on real floorplans (MI300 / 5G-SoC / CoWoS configs), 9–18 dB realised mean S21 / 27 dB peak across band.

Synopsys

arrow_forward

EDA-ready signoff outputs

HFSS, Sigrity, SPICE, GDSII exports. 23 commercial glasses × 3 metals × geometry sweeps.

Cadence

arrow_forward

Sigrity-importable PDK + customer-side native signoff

Genesis-side CSV roundtrip cert (5 pytest contracts, 50-cell grid stress, 0e0 floating-point error). Cadence-native validation cleanly deferred per documented workflow lock — same AGI/Sigrity/Apache pattern.

Marvell

arrow_forward

Custom-silicon glass-substrate workflow lock

Custom Compute (Trainium-class HBM4 stacks) + Optical Interconnect (post-Celestial AI $5.5B defensive M&A) + Networking SoC (mmWave 224G+). 5/5 EDA adapters + 5/5 multi-solver-verified golden kits + R²=0.9999966 surrogate.

Nvidia

arrow_forward

HBM4 + Blackwell+ glass interposer signoff

BEM-vs-Palace μ-correction cal head for the HBM4 corner (90.3% gap closure, latest retrain 2026-05-05). Part of the 6/6 per-regime calibration coverage now live in 3 API routers. The only glass-substrate impedance signoff surface the rest of the EDA industry hasn't built.

AMD

arrow_forward

Instinct MI400+ glass-substrate workflow lock

Instinct MI400+ HBM4 stacks + Versal AI Edge/Premium + Pensando+Enosemi DPU/Optical — three product lines that hit glass substrates by 2027. Defensive M&A pattern continues post-Enosemi (May 2025). 5/5 cross-EDA-vendor workflow lock + HBM4 cal head.

Apple

arrow_forward

M-series + Vision Pro glass-substrate workflow

M5/M6 multi-die packaging + Vision Pro micro-OLED-on-glass + post-Apple-Intelligence custom AI silicon — three product lines on glass substrates by 2027-28. Apple controls its silicon stack end-to-end except packaging EDA; ChipletOS unifies that signoff across all 5 EDA vendors.

TSMC

arrow_forward

InFO-Glass + CoWoS-G + 3DFabric+ workflow lock

Foundry-side glass-substrate process flow signoff. Per-foundry fab-coupon export with 12-layer stack-up profiles (Amkor / MOSIS / generic; TSMC InFO-Glass / CoWoS-G profiles available under MNDA), GDSII + IPC/SEMI DRC + cross-EDA-vendor portability.

Samsung Foundry

arrow_forward

I-Cube + H-Cube + 3D-IC glass roadmap

I-Cube-G + H-Cube-G migration competing with TSMC CoWoS-G. HBM4 stacks + 3D-IC custom-foundry per-customer flows. Customer-EDA portability across Cadence/Synopsys/Ansys/Keysight/Siemens — Samsung's hyperscaler customers can hand you a Genesis bundle from ANY of those EDA stacks.

Qualcomm

arrow_forward

Snapdragon X + Cloud AI 100 + 5G/6G mmWave on glass

3 strategic product lines on glass substrates by 2027-28. Snapdragon X compute (PC chiplet packaging) + Cloud AI 100 (HBM4 inference accelerator) + 5G/6G mmWave RF (24-77 GHz). golden_mmwave_77ghz kit + HBM4 cal head + UCIe cal head all aligned to Qualcomm's three product lines.

Absolics

arrow_forward

Panel-level glass workflows

Bondability calibration on real wafer maps (WM-811K), CMP recess + overlay σ uncertainty bands, lot-intelligence verdicts.

Load-bearing

7 platform achievements every buyer package shares

The same surrogate, calibration, coverage, and audit infrastructure underlies every buyer package above. Verifiable in 5 min on a fresh clone via bash scripts/audit/buyer_verify.sh.

Production surrogate model
R²=0.9999966 · MAPE=0.0292%
6.75M-row strict-grouped BEM corpus, geometry-disjoint train/test split, HBM4 test MAPE 0.0154%.
Per-regime cal heads (6/6)
UHF 90.5% · HBM4 90.3% · pooled 17→4.7%
First successful cross-physics μ-correction on glass interposers anywhere. Latest retrain (2026-05-05): UHF 90.5% · HBM4 90.3% · WIDE_PITCH 87.6% · UCIE 81.6% · EXTREME_TIGHT 50.6% · MMWAVE 43.4% gap closure. 4/6 elite (>80%). Palace is full-wave FEM cross-physics truth, not VNA measurement.
Conformal coverage
94.4–95.4% empirical · 95% nominal
Distribution-free Palace-truth coverage interval on every prediction. HBM4 q=8.38 Ω · UCIE q=6.03 Ω · EXTREME_TIGHT q=35.10 Ω · WIDE_PITCH q=9.84 Ω · pooled q=9.11 Ω. DD-defensible.
Cross-physics envelope
6.73% median · 10.33% max
100-geometry × 4-frequency Palace witness — first quantification of the BEM-quasi-static-vs-full-wave physics ceiling on glass TGVs. The reference frame for every cross-physics claim.
Production API stack
~30 live endpoints · 30 MCP tools · 10 agents
predict-impedance · tgv-signoff · geometry-from-target · geometry-pareto · drc-validate · validate-against-measurement · export-fab · cross-solver-matrix + 22 more. Real, deployable, route-backed.
Universal diff-pair scaling law
log(Z₀_diff)=0.338·log(sep/d) · R²=0.918 · n=2.1M
Exponent 0.338 universal across 5 commercial glasses (AF32, Borofloat33, EN-A1, Eagle XG, Fused Silica) to 0.001. Now Apache-2.0 OSS as pip install glass-tgv-diffpair. DAC 2026 paper drafted.
Adjoint-BEM cross-physics gradient
r_pooled = 0.99984 (n=20)
Empirical proof that surrogate-gradient direction matches BEM physics gradient — what makes inverse design fast AND physics-grounded. Per-component r_d=0.998 · r_p=1.000 · r_t=0.969 (t-component disclosed honestly).
Track A end-to-end + 3/5 cross-solver matrix
composite lab_readiness_score 0-100 + verdict bands · BEM ✓ Palace ✓ FastHenry2 ✓ · OpenEMS / gprMax honest skip
Single buyer-facing 0-100 score (send_to_lab ≥95 / send_with_extra_qc 80-94 / hold 60-79 / reject <60) on every prediction surface. Cross-solver matrix at 3 of 5 wired (BEM always-available + Palace full-wave FEM + FastHenry2 inductance solver, Z₀ via L_FH + analytical-coax C honestly disclosed as hybrid; 4/5 spot-checks added at 1-geom and 10-geom scale). 4 fabricated proxy values caught + fixed in audit pass — NO synthetic data anywhere; gates without measured signals contribute None and trigger partial_score=true rather than fabricated values.
Full canonical reference and Track A details available under NDA in the data room.