Independent technical memo · May 2026
Why Silicon Photonics
800G / 1.6T datacenter optical, automotive LiDAR, AI-training-cluster optical fabric — the silicon-photonic IC market is doubling into AI infrastructure, and the design tools haven't followed. ChipletOS Photonic Signoff is the AI-native distribution layer the Lumerical / Omnisim / ANSYS stack doesn't ship.
One platform, two markets: chiplet packaging (today) and silicon photonics (alpha today, with the full build-out on the roadmap). Same surrogate stack, same validation suite, same cross-vendor exporter discipline.
Market thesis
Three inflection points pulling photonic IC into AI infrastructure
800G / 1.6T datacenter
Hyperscale 800G transitioning to 1.6T per port; co-packaged optics (CPO) is the inflection. Per-die optical IC iteration cycles scale with signoff turnaround — exactly where AI-native surrogates compress the loop.
Automotive LiDAR
Solid-state LiDAR phased-array signoff is fundamentally a grating-coupler + photonic-crystal + waveguide-router problem. All three primitives ship with a v1 trained AI surrogate at ≥ 99% R² vs reference solver; a higher-fidelity refresh is on the roadmap.
AI-cluster optical fabric
Training-cluster optical interconnect (NVIDIA, Marvell, Acacia/Cisco, Lumentum) is the largest single optical-IC market today. Same MCP / Cursor / Claude.ai distribution wedge the chiplet stack uses — applied directly to optical-fabric signoff.
Five named customers
Marvell · Intel · NVIDIA · Acacia (Cisco) · Lumentum
The named acquirer / customer set for the Photonic Signoff sub-brand. Each entry maps to a specific 2026-2027 product roadmap where AI-native distribution plus closed-loop synthesis plus a trained AI surrogate against a full-wave reference solver compresses the signoff loop.
Marvell SiPh
800G / 1.6T DSP-attached silicon photonics for hyperscale optical interconnect. Closed-loop synthesis plus a trained AI surrogate against a full-wave reference solver accelerates per-die optical-IC iteration cycles.
Intel Foundry (Photonics)
Glass + silicon photonic interposer fabs. ChipletOS chiplet-stack already covers glass-TGV signoff; photonic sub-brand adds the optical-IC layer through the same audit gates.
NVIDIA (Optical)
Co-packaged optics (CPO) for AI-training cluster fabric. Cluster-scale optical-IC characterization is exactly the multi-primitive (waveguide / MZI / MMI / ring / grating) signoff surface the sub-brand ships.
Acacia (Cisco)
Post-acquisition Acacia (Cisco) coherent-optical line cards. Lumerical / Omnisim license costs scale per-seat; AI-native distribution + per-prediction conformal CI reduces sim turnaround on every coherent-modulator iteration.
Lumentum
Datacenter transceivers + LiDAR for automotive optical. Grating + ring + photonic-crystal primitives map directly to LiDAR phased-array + DWDM transceiver signoff.
Why ChipletOS Photonic Signoff specifically
AI-EDA distribution + closed-loop synthesis + trained AI surrogate against a full-wave reference solver
None of these four pillars ship today in Lumerical, Omnisim, or ANSYS Lumerical-FDTD. The sub-brand inherits the chiplet stack's audit-gate + retraction-registry + buyer-DD-runnable harness discipline and re-applies it on day one.
AI-EDA distribution wedge
Same MCP / Cursor / Claude.ai distribution layer the ChipletOS chiplet stack already runs on — applied to silicon photonics. Lumerical doesn't ship one. Photon Design Omnisim doesn't ship one. ANSYS Lumerical-FDTD doesn't ship one. SI/PI/PIC engineers using AI assistants get the Photonic Signoff stack by default.
Closed-loop synthesis (v1 live for 5 of 6 primitives)
Inverse-design endpoints already wired for waveguide (Neff → width/height) and ring (FSR/Q → radius/coupling). Our v1 release ships a trained AI surrogate (MLP) at ≥ 99% R² vs reference solver for MZI / MMI / ring / grating / photonic crystal. Waveguide stays on the closed-form analytical model today; a higher-fidelity refresh is on the roadmap.
Trained-surrogate roadmap against full-wave reference
Per-primitive architecture choices: trained AI surrogate (MLP) for waveguide / MMI / grating, Conv1D-MLP for the MZI spectrum, FNO for ring resonance, GraphSAGE for photonic-crystal lattice. All trained against the full-wave reference solver. Native solvers do not belong in optimizer inner loops — a lesson the chiplet platform learned the hard way and the photonic sub-brand inherits on day one.
Same validation suite as the chiplet stack
Five photonic validation checks wired into the validation suite: trained-surrogate accuracy (validation suite check passes), AIM-Photonics-class design-rule check (live), cross-solver agreement (on the roadmap), published-paper cross-check (live), and an adversarial robustness harness (live). One platform, two markets — same drift sentinel, same retraction registry, same buyer-DD-runnable harness.
Scope
What is real today vs what is on the roadmap
Disclosed gaps
- Trained AI surrogate LIVE for 5 of 6 primitives at ≥ 99% R² vs reference solver. Waveguide remains on the closed-form analytical model today; a higher-fidelity refresh is on the roadmap.
- Vendor-native validation on the roadmap — Lumerical .lsf / Omnisim XML / ANSYS INI / KLA Kandela XML / GDSII export bundles are self-consistent but bit-perfect native cert requires a customer-side Lumerical / Omnisim license.
- Validation suite checks live today: trained-surrogate accuracy, design-rule check, published-paper cross-check, and adversarial robustness harness. Cross-solver agreement is on the roadmap.
- Photonic VNA wet-lab campaign queued — mirrors the chiplet $200-500K wet-lab RFQ pack pattern.
See Trust & Validation for the full validation-suite methodology, published-paper cross-check numbers, and the retraction registry.
Try the photonic alpha or read the architecture
Three public Modal endpoints + eight auth-gated routes. Same audit pattern as the chiplet stack — applied to silicon photonics.