Pre-compliance screening

Interface signoff,
on glass.

Four channel-budget checkers for the most common chiplet/package interfaces, all driven by ChipletOS BEM multi-conductor Z₀ extraction. Each call returns a per-check pass/fail with margin in dB or Ω, the frequency-resolved insertion-loss curve along the route, and an explicit provenance tier.

Pre-compliance screening, not certified compliance. Spec windows are paraphrased from public specifications (UCIe 1.1, PCIe 6.0 base, IEEE 802.3ck/df draft, JEDEC HBM4) for screening purposes. Use this surface to rank package candidates; use Palace 0.16.0 full-wave verification + a fabricated VNA coupon for signoff.

Open the dashboard →API reference
UCIe 1.1 (2023)

UCIe Advanced & Standard

  • Z_diff window: 80–90 Ω (Advanced) · 85–95 Ω (Standard)
  • Frequency band: 4–32 GHz (Advanced) · 2–16 GHz (Standard)
  • Insertion-loss budget: −3 dB (Advanced) · −5 dB (Standard)
  • Bump-pitch / lane-length checks against package class
POST /v1/interface-signoff/ucie
JEDEC HBM4 (8 Gbps/pin, 1024-bit)

HBM4 12-Hi escape

  • Z_se 50 Ω ± 5 Ω at 4 GHz Nyquist
  • Insertion loss budget: −6 dB at Nyquist
  • Escape pitch ≥ 35 µm, rows-needed feasibility
  • Warpage proxy from stack height + hotspot density + glass thickness
POST /v1/interface-signoff/hbm4
PCIe 6.0 base (2022)

PCIe Gen6 (PAM4 64 GT/s)

  • Z_diff 85 Ω ± 10 %
  • Package portion of 32 dB insertion-loss budget at 16 GHz Nyquist
  • FEXT crosstalk guidance ≤ −40 dB
  • Tunable lanes / route length / bump pitch
POST /v1/interface-signoff/pcie-gen6
IEEE 802.3ck/df-style budget split

800G SerDes (8×112 GT/s PAM4)

  • Z_diff 92 Ω ± 7 Ω
  • 18 dB package insertion-loss budget at 28 GHz Nyquist
  • FEXT crosstalk guidance ≤ −45 dB
  • 8 lanes default, configurable to 32
POST /v1/interface-signoff/800g

What runs under the hood

Z₀ / Z_diff

BEM multi-conductor quasi-static extraction from the Glass PDK. Single-line Z₀ and pair-line differential Z derived from the RLGC matrices for the requested glass / TGV / dispersion combination. Calibrated against IEEE-published HFSS-coaxial reference points (3.53 % MAE) and 100 Palace 0.16.0 full-wave runs (105-point cross-check).

Insertion loss

Per-meter attenuation from γ = √((R + jωL)(G + jωC)), aggregated analytically along the requested route length. Returned as a per-frequency curve and as IL at the spec Nyquist.

Crosstalk / warpage

FEXT proxy from pair-line mutual L/C ratio at the band edge. HBM4 warpage is a proxy from stack height, hotspot density, and glass thickness — explicitly labelled "analytical proxy, not measured warpage signoff."

Honest framing

  • All published Z₀ references inside our literature corpus are tagged source_type: simulation (HFSS-coaxial extractions). No Z₀ in our corpus is from a VNA today; a ~$200–500 K wet-lab coupon-pack campaign is queued.
  • "UCIe-style screening" is not the same as a UCIe Compliance Working Group certification. We screen against the spec windows; we do not certify.
  • Channel budget is package-portion only. Add board / silicon / equalizer budgets from your own toolchain to close the link.