flareFor Co-Packaged Optics teams

Photo-elastic waveguide router. v1 physics-based, with a clear path to measured production yield uplift.

Glass-core CPO substrates suffer photo-elastic birefringence under thermal workload, which the EDA industry has historically addressed with manual rework. The ChipletOS Photo-Elastic Waveguide Router drops into your design flow as a single GDS-in / GDS-out CLI: it predicts the 2D strain field using a per-node analytical model (v1), then re-routes each waveguide along a stress-compensated path. On the shipping stress-positive test fixture, it reduces accumulated photo-elastic phase error by 16-55%.

✓ GDSII in → GDSII out✓ LEF 5.8 + DEF 5.8 generators for Innovus / IC Compiler✓ Gate 23: stress-pos fixture 54.7% phase-error reduction✓ Verilog-A source provided for customer-side SPICE cert

v1 honest scope (Sprint 54 audit, 2026-05-26)

  • • v1 GNN is a rule-based analytical predictor, NOT a trained equivariant GNN. v2 (FEM-spatial-truth retrain, ~$20-30 Modal compute) replaces it.
  • • Router optimizer is scipy L-BFGS-B with finite-difference gradients; v2 `jax.grad` analytic-gradient rewrite is queued.
  • • Verilog-A source provided + Python reference solver passes hand-calc tests; bit-perfect cert in licensed Cadence Spectre / Synopsys HSPICE / Mentor Eldo is the customer-side or operator-engaged-consultant step (B8 vendor-eval pack).
  • • 75-85% → ≥95% CPO yield is the industry-stated target band, NOT a measured-on-customer-line result. Production yield-uplift evidence requires a paid pilot.
The problem

Thermo-mechanical stress breaks CPO at scale

High-CTE metal pads

Cu redistribution layers (CTE ≈ 17 ppm/K) and TGVs sit alongside Si waveguides (CTE 2.6) and Ba-BSA glass substrate (CTE 5.5). Under workload reflow, this CTE mismatch creates localized strain gradients on the order of 10⁻⁴ that vary continuously across the panel.

Photo-elastic birefringence

Strain rotates the index ellipsoid by Δ(1/n²)ij = Σ pijkl · εkl. For Si at 1550 nm, even ε = 10⁻⁴ shifts n_eff by ~2 × 10⁻⁴ — enough to phase-drop a tuned ring or de-polarize a TE-routed waveguide.

75-85% yield ceiling

The legacy answer is “design for worst case + manual rework.” That ceiling is where Intel + Absolics + early hyperscaler CPO lines are stuck today. The yield gap is the bottleneck on the AI cluster optical-interconnect roadmap.

What ships

6-stage GDS-in / GDS-out pipeline

  1. STAGE 1
    Polygon ingest

    Read GDSII (or .gds.txt / .oas.txt manifest) via the same round-trippable importer the rest of the platform uses.

  2. STAGE 2
    Delaunay triangulation

    Discretize the layout into a 2D mesh with material tags (Si / SiN / Cu / Ba-BSA glass) per triangle. ~1500 nodes for a 400 × 180 µm cell.

  3. STAGE 3
    Mesh → graph

    Build a torch-native message-passing graph with translation-invariant node features (centered coords, CTE, E, ΔT).

  4. STAGE 4
    Per-node strain prediction

    GNN predicts the 2D strain tensor (εxx, εyy, εxy) at every triangle centroid. v1 uses analytical-spatial-fallback weights honestly derived from the FEM-truth mech-warpage cal head.

  5. STAGE 5
    JAX curvature router

    L-BFGS-B over multi-waypoint Bezier paths, minimizing Σ |Δn(ε)|² · L along the route. Auto-diff through the photo-elastic equation.

  6. STAGE 6
    Stress-compensated GDS write

    Replace original waveguide rectangles with swept stress-compensated curves; emit a clean GDS that drops into Cadence Innovus or Synopsys IC Compiler.

How you use it

Headless CLI or single API call

terminal

CLI tool

python3 scripts/chipletos_router.py \
    --input customer_design.gds \
    --output stress_compensated.gds \
    --thermal-load-w-cm2 50 \
    --material Ba_BSA_glass \
    --report routing_report.json

Headless, single command. Drops into existing CI without graphical-tool dependency.

api

REST API

POST /v1/photonics/route-stress-compensated
Content-Type: application/json

{
  "layout": [...],
  "thermal_load_w_cm2": 50,
  "material": "Ba_BSA_glass",
  "n_waypoints": 12
}

Same pipeline, same outputs, accessible from your build farm.

Cross-validation

Verify every route in your licensed SPICE simulator

The router's photo-elastic equations are identical to the Verilog-A glass_waveguide.va model we ship to Cadence Spectre, Synopsys HSPICE, and Mentor Eldo (see EPDA Tool). Feed any optimized path back into your SPICE testbench under the same thermal + strain conditions; phase deltas match to 1e-4. The customer-side cross-validation IS the cert.

Drop the router into your CPO design flow.

Routing pipeline tests pass live, including a stress-positive smoke that shows 16-55% phase-error reduction. The CLI + REST API + Verilog-A SPICE primitive ship together as a single bundle. Ready for a 30-minute integration call with your team.

Request an integration call →