What it shows
A via is a short vertical metal connection through the carrier that joins the chips in a package. A common fast model treats each via as an endlessly long rod and solves only a flat slice across it. Engineers call this a two-dimensional, per-unit-length model. A real via has a top and a bottom, and the electric field spreads out at each end. A flat slice cannot see that, by construction. That flat models miss the ends is well known, and an outside three-dimensional solver such as FastCap can already size it.
How we measured it
We built our own three-dimensional solver to measure that share. Before using it, we checked it against shapes with exact textbook answers (one sphere, two spheres and a short coaxial cable) and against FastCap on a group of 8 vias. The record gives the size of each of those checks:
The published record says, word for word (an excerpt)
Validated before use against sphere 2.8e-16, two-sphere Kelvin 3.1e-7, finite-coax 2.7e-7, long-via→2-D-spectral slope 5.4e-5, and an independent FastCap N=8 cross-check at 0.80% diagonal / 1.04% dominant off-diagonal.
For one simplified via, described under the limits below, about 40% of the capacitance, measured with the via driven as one of a pair, sits at its ends. The record’s words for what that share is:
The published record says, word for word (an excerpt)
3-D end-effect that a 2-D per-unit-length model structurally omits — measured with our own 3-D solver, validated against exact references before use.
Adding the ends back to one flat solver
We then added the end term, solved by our three-dimensional solver for each layout, to one of our flat solvers, the spectral pair solver, as a correction it cannot skip: if the correction is missing, the solver refuses to return a number. FastCap graded the result on 86 via pairs from 12 fresh layouts. With the correction, the worst error was 0.498% and the median error 0.308%. Without it, the median error was 42.794%.
The published record says, word for word (an excerpt)
Applied as a blocking correction to the 2-D spectral pair solver, it brings that solver within 0.498% (max) and 0.308% (median) of FastCap on 86 pairs of 12 fresh layouts drawn from a pre-registered seed, against a 42.794% median error uncorrected.
Why it matters
Design software needs a fast estimate of the coupling between vias, because a full three-dimensional solve of every candidate layout is slow. A flat model gives that speed, and its blind spot sits at the ends of each via. On the layouts tested, a correction measured by a three-dimensional solver closed that gap for one solver, at the cost of one three-dimensional solve per layout.
Why now: chip makers are moving to packages that hold several chiplets, and Intel has announced glass substrates for such packages, planned for the latter part of this decade. More of the coupling a design team must estimate sits between the vertical connections of those carriers.
What is ours, and what is not
The end effect itself is textbook physics, and FastCap can measure it. What is ours is a three-dimensional solver checked against exact answers before use, the measured share, and its use as a correction that one flat solver must apply before it returns a number.
Who should care
- Chip-package and interposer design teams. Ask whether the fast coupling model behind your margins includes the ends of the vias, and ask to see it graded against a three-dimensional solver on your own geometry.
- Makers of extraction software. A flat model is a reasonable fast path. A measured end term, graded against an outside solver, is one way to close its known gap.
The limits, in the record’s words
The published record says, word for word (an excerpt)
It is not wired into certificate issuance, and the other 2-D solvers (MoMSolver2D, batched_mom) still omit it.
The published record says, word for word (an excerpt)
FastCap runs on the lab's own panelling, and its own coarse-to-graded change reaches 0.53%, the size of the corrected solver's worst error, so agreement finer than ~0.5% is not resolved.
The published record says, word for word (an excerpt)
The bars were chosen after a three-geometry probe (disclosed in the prereg); the 12 layouts were drawn only after the prereg was committed.
In plain words:
- The share of about 40% is for one simplified via shape, measured in simulation. On another geometry the share can differ.
- The checks cover groups of up to 8 vias.
- The correction is in one flat solver only. Our other flat solvers still leave the ends out, and our design-check certificates do not use the correction.
- FastCap ran on our own surface mesh of the shapes. When that mesh was refined, FastCap’s own answer moved by up to 0.53%, about the corrected solver’s worst error, so agreement finer than about 0.5% is not resolved.
- The pass bars were set after a trial on three geometries, which the record discloses; the test layouts were drawn only after the bars were committed.
- Every comparison here is one simulation against another, not a measured package.
Open source for this step
Tools and datasets we publish for the package step of building a multi-chip package. They are the checkers around this work, not a copy of the result itself.
- physics-lint: One command that checks a folder of physics models against a fixed set of named physical rules, with findings straight into CI.
- maxwell-lint: Flags a coupling extractor whose answers no passive set of conductors could produce.
- sparam-lint: Is your signal-response model physically possible? Five physical laws checked from the command line.
- interval-core: The interval arithmetic core behind our proofs over whole families of layouts.
- touchstone-tools: Read, write and convert Touchstone files, the standard text files that record how signals pass through a package's connections, and refuse to write one that cannot be read back.
- physics-lint-mcp: The physics checks, callable by an AI agent.
- physics-lint-action: A GitHub Action that fails the build when a model breaks one of a fixed set of named physical rules.
- Signal-response validity corpus: A labelled corpus of physically invalid signal-response networks, and a scorer that grades any checker against it.
- screening-ceiling: The screening-ceiling family as an open dataset.