What it shows
A chip package joins several small chips. Inside it, metal connections run vertically through a glass or silicon carrier, and neighbouring connections pull on each other electrically. Design software needs a fast estimate of that coupling, because a full field solve of every layout is slow.
One simple estimate takes the connections two at a time and adds the results up. Our predictor models the whole group at once. For capacitance we used outside referees: FastCap, a public three-dimensional solver, and Palace, an open-source finite-element code. Inductance still comes from our own solver, as the limits below explain.
In the record, the predictor is called the many-body operator and the baseline is called pairwise superposition. Its claim, in an excerpt:
The published record says, word for word (an excerpt)
the many-body operator beats pairwise superposition on every sampled population measured
The sampled populations are:
- three samples graded by FastCap, kept side by side in the record;
- one narrow slice graded by Palace.
The fairest is the one where FastCap supplies both the add-up-the-pairs baseline and the right answer, on held-out layouts; the comparison record counts most of them, not all, as its confirmatory set. For each of those layouts we took the size of the error in the coupling terms, once for the baseline and once for the predictor, both measured against FastCap’s full solve, and divided the first by the second. The middle value of those ratios is 6.1172: the predictor’s error was that many times smaller. The larger margins on the home page use our own pair-by-pair solver as the baseline, so they are not like for like.
Why it matters
Without an outside referee, every accuracy figure for a fast predictor is graded by software its authors wrote. A buyer’s reviewer cannot treat that as independent. A referee with no stake in the answer turns an assertion into a measured comparison, for the layouts tried.
Why now: chip makers are moving to packages that hold several chiplets, and Intel has announced glass substrates for such packages, planned for the latter part of this decade. More of the coupling a design team must estimate sits between the vertical connections of those carriers.
Who should care
- Makers of fast extraction tools. The comparison shows a whole-group model tracking FastCap more closely than a pairwise sum, on these layouts. Ask for the same comparison on yours.
- Package signal-integrity teams. Read it as evidence on capacitance between vertical connections, not on the full electrical behaviour of a package.
The limits, in the record’s words
The record’s own limits note is not published here, because it is written in our internal notation. The limits we rely on are stated in plain words below, with an excerpt of its scope field.
It covers capacitance only. The other half of coupling, inductance, still comes from our own solver, because the outside inductance solver we tried did not return a usable answer on these layouts. So the reference answer is part outside solver, part our own, and it is not a full electromagnetic simulation.
The published record says, word for word (an excerpt)
Palace is 4.781× on 18 geometries, a single coupling-heavy slice with 85 of 103 points excluded. Both are simulators, not silicon.
It does not show that the margin holds on layouts outside the samples. Whether a pairwise sum reflects what production extraction tools do is a separate question; here it is a baseline, not a named product. The solver runs are recorded by fingerprint in the evidence file, and the runs themselves cannot be redone from this site.
Open source for this step
Tools and datasets we publish for the package step of building a multi-chip package. They are the checkers around this work, not a copy of the result itself.
- physics-lint: One command that checks a folder of physics models for predictions that break basic physics, with findings straight into CI.
- maxwell-lint: Flags a coupling extractor whose answers no passive set of conductors could produce.
- sparam-lint: Is your signal-response model physically possible? Five physical laws checked from the command line.
- interval-core: The interval arithmetic core behind our proofs over whole families of layouts.
- touchstone-tools: Read, write and convert N-port Touchstone files, and refuse to emit one that cannot be read back.
- physics-lint-mcp: The physics checks, callable by an AI agent.
- physics-lint-action: A GitHub Action that fails the build when a model predicts physics that cannot exist.
- Signal-response validity corpus: A labelled corpus of physically invalid signal-response networks, and a scorer that grades any checker against it.
- screening-ceiling: The screening-ceiling family as an open dataset.